The present invention pertains to the testing of integrated circuits and the like. More specifically, the present invention relates to an on-chip debug system used for functional testing of integrated circuits.
Integrated circuits, including processors such as CPUs and the like, require substantial testing, referred to as debugging, in order to assure proper functioning. As integrated circuits become faster and more complex, the need for thorough functional testing becomes even more important.
A number of techniques have been used to provide debug support for an integrated circuit that includes a processor. One such approach utilizes dedicated on-chip logic to provide, for example, a series of break points. A break point is a point in the control flow of the processor that allows the processor execution to be modified. For example, break points can trigger a number of possible events, such as halting the processing in order, for example, to enter a debug monitor mode as well as a monitor mode, etc. The control flow of a device is typically those instructions used by the microprocessor, for example, to execute a particular function. Once the processor has entered the debug monitor mode, execution of the control flow is halted and the processor is put in communication with an external emulation system. Once in communication with the emulation system, a user can view the execution of the processor at the particular break point. By way of example, if a memory transaction is performed at a particular address, that same memory transaction can also be entered into the emulation system and, in turn, viewed by the user.
Conventionally, the chip manufacturer has taken one of two approaches to implementing on-chip logic debug support. In one approach, the chip manufacturer produces 2 variants of the same chip, one production version to be sold and one test chip version dedicated to emulation testing. Unfortunately, using two variants of the same production chip substantially increases the cost of manufacture since all production chips must be duplicated and the test chip will never be sold (producing no revenue for the chip manufacturer). In another approach, the chip manufacturer can implement on-chip logic debug support by dedicating a portion of the production chip real estate to the logic elements required to define the required break points. Unfortunately, dedicating a portion of the production chip real estate to on chip debug support increases design time and adversely impacts the designer""s ability to shrink the size of the chip. In addition, in order to minimize the amount of production chip real estate dedicated to on-chip logic requires that the amount of on chip logic be commensurably reduced. This reduction in on chip logic has the effect of reducing the capability of the on-chip logic to adequately provide the necessary debug capabilities. Therefore, in order to compensate for this reduction in on chip debug support, external testers are typically employed greatly increasing the post fabrication back end costs.
Another technique used to provide debug support for a processor is referred to as real time tracing. The real time trace provides the user with the capability to view selected internal bus and selected internal data transactions of the processor during operation. Typically, providing access to the internal busses and internal data transactions requires use of a dedicated bond out chip. Generally, the dedicated bond out chip is formed of a standard production chip with added external busses used to provide the necessary connections to the device under test that allow access to the selected internal busses and data registers. Unfortunately, as the size and complexity of the chip increases, the number of bond out pads required of the dedicated bond out chip increases dramatically. Since the number of bond pads may be limited by the size of the dedicated bond out chip, the amount of information available using the real time trace technique may be reach a practical limit in very large and/or very complex chips. Just the opposite of what is desired with these type devices. In addition, as the speed of the integrated circuits increase, the amount of data in the form of information bits per test cycle increases dramatically. This increase in information rate can exceed the capacity of the emulator and/or any intervening data busses.
In view of the foregoing, it should be apparent that improved on-chip debug systems would be desirable.
An improved on-chip debug system used to provide debug support for integrated circuits as well as methods for debugging such integrated circuits are described. More specifically, the debug support system is arranged to provide a selected subset of all possible data bands generated by the integrated circuit under test as needed.
In one embodiment of the invention, an integrated circuit useful for selectively providing operational test data of selected internal components is disclosed. In response to control signals, the electrical components generate operating data in the form of data bands. The data bands are used to evaluate the functionality of the integrated circuit. The integrated circuit includes a plurality of I/O lines suitably arranged to couple the electrical components to external circuitry. In response to a test program, the external circuitry provides control signals capable of directing selected electrical components to generate associated data bands. The integrated circuit also includes a data band selector connected to the plurality of electrical components. The data band selector is used for selecting certain ones of the data bands as directed by the control signals based upon instructions included in the test program.
In another embodiment of the invention, the integrated circuit is a system on a chip type integrated circuit.
In yet another embodiment of the invention, an on-chip debug system suitable for functional testing of an integrated circuit is disclosed. The on-chip debug system includes a host computer arranged to perform executable instructions, an emulator connected to the host computer arranged to generate control and logic signals based upon instructions received from the host computer, and a device under test (DUT) integrated circuit connected to the emulator responsive to the control and logic signals generated by the emulator. The device under test (DUT) integrated circuit includes a plurality of electrical components certain ones of which respond to external signals by generating an associated data band indicative of a particular operational characteristic of the electrical component. The device under test integrated circuit also includes a programmable data band selector connected to the certain electrical components. The programmable data band selector is arranged to output selected ones of the data bands based upon control signals received from the emulator by way of a data band selector control line.
In still another embodiment of the invention, the debug system includes a master target board connected to the emulator having a master DUT integrated circuit integrally connected therein, as well as a slave target board connected to the emulator having a slave DUT integrated circuit integrally connected therein. The debug system also includes a comparator connected to the master target board and the slave target board that is used to assure that the master DUT and the slave DUT are operating in synchrony.
In another aspect of the invention, an integrated circuit is disclosed. The integrated circuits includes a plurality of electrical components responsive to external signals to generate data bands, the data bands being operational information. The integrated circuit also includes a data band selector connected to the plurality of electrical components arranged for selecting certain ones of the data bands as directed by control signals generated by external circuitry.
In still another aspect of the invention, a method of debugging an integrated circuit using an on-chip debug system is disclosed. The on-chip debug system includes a host computer arranged to perform executable instructions, an emulator connected to the host computer arranged to generate control and logic signals based upon instructions received from the host computer, and a device under test (DUT) integrated circuit connected to the emulator responsive to the control and logic signals generated by the emulator, the device under test (DUT) integrated circuit includes a plurality of electrical components wherein certain ones of the electrical components respond to external signals by generating an associated data band indicative of a particular operational characteristic of the electrical component, and a programmable data band selector connected to the certain electrical components arranged to output selected data bands based upon control signals received from the emulator by way of a data band selector control line. The testing is performed by selecting a data band to be traced and selecting a break point used to view operational characteristics of a particular parameter at a specific location in a control flow of the DUT integrated circuit. Loading a test program into the emulator, executing the test program, capturing the selected data band, and capturing result data if the break point has been detected. Next, post processing the captured data band, and repeating the method until all data bands have been captured and post processed.